1. Field of the Invention
The present invention relates generally to computer hardware and, more specifically, to a system and method for autonomously power-gating an idle core in a multi-core system.
2. Description of the Related Art
In a multi-core processing environment, an operating system distributes tasks for execution to multiple cores within the processing environment. When a core processes the tasks received from the operating system, the core becomes idle. An idle core wastes power because the core is not executing any tasks but is still turned on and consuming power. In devices where power is a limited resource, for example in mobile devices, such wastage of power is highly undesirable.
One solution to the above-mentioned problem involves the operating system recognizing that the core has become idle and causing the core to be powered down. In this approach, the operating system is heavily involved in determining when to power down the core and power up the core. Further, the operating system stops scheduling work on the powered down core and migrates threads that were previously executing on the powered down core to other cores within the processing environment. These operations performed by the operating system impose an undesirably high processing and time penalty for entering and exiting the powered down state.
As the foregoing illustrates, what is needed in the art is an improved technique for powering down idle cores that overcomes the drawbacks associated with conventional approaches.